1. Field of the Invention
The present invention relates to a single photon avalanche diode.
2. Description of the Related Art
An avalanche photodiode can be operated differently according to a selected mode. When the selected mode is Geiger mode, the avalanche photodiode operates under a reverse bias voltage higher than its breakdown voltage. When the selected mode is linear mode, the avalanche photodiode operates under a reverse bias voltage lower than the breakdown voltage. The avalanche photodiode operating in the Geiger mode is referred to as a single photon avalanche diode (SPAD), which is superior in some characteristics to the avalanche photodiode operating in the linear mode. The SPAD is capable of generating an electric signal in response to an input of very small optical power, such as a single photon, and can be employed as a device dedicated to detecting the single photon. Further, the SPAD has a higher time resolution (approximately several ten ps) that is sufficiently responsive to detect an optical event with high precision. The above-mentioned advantageous characteristics are suitable to realize time measurement for a weak optical signal, such as in the so-called time of flight (TOF) principle.
A large-scale array structure, such as an image sensor, can be realized by implementing the SPAD using a semiconductor integration technology, such as a CMOS process technology. A large-scale array structure including several tens of thousands of SPADs disposed in a two-dimensional pattern has recently become available.
However, the aperture ratio of a SPAD array is small compared to that of a two-dimensional array structure of a conventional diode. The aperture ratio is the ratio of the light sensitive area to the entire area of the pixel.
FIG. 10 illustrates a cross-sectional structure of a conventional SPAD that can be realized using a CMOS process technology. A first semiconductor layer 101 is an implanted layer positioned on a second semiconductor layer 102 of opposite-conductivity type. The first and second semiconductor layers form a p-n junction 110. The second semiconductor layer 102 is an epitaxial layer formed on a substrate 108 of an integrated circuit, or on another implant layer or substrate. A separation layer 103 is an implanted layer that surrounds each SPAD in such a way as to separate the SPAD from a neighboring SPAD and circuit elements in the lateral direction. The separation layer 103 is of opposite conductivity type to the first semiconductor layer 101. The p-n junction includes electrodes 104 and 105. A depletion layer 106 is formed in the SPAD when a reverse bias is applied to the p-n junction.
To use the SPAD as a single photon detector, it is necessary to form a high electric field area 107 of approximately 3×105 V/cm, which should be uniformly formed to have a planar structure that underlies the first semiconductor layer. More specifically, it is necessary to form an avalanche multiplication area. When carriers generated by the photoelectric effect reach the avalanche multiplication area, the carriers are multiplied while they repetitively cause impact ionizations. The multiplication speed is faster than the charging speed of the junction capacitance of the SPAD. Therefore, the junction capacitance of the SPAD can be completely discharged. In other words, incident light can be extracted as a large signal without requiring external amplification.
A major challenge in designing the SPAD is the difficulty of forming the high electric field area (more specifically, the avalanche multiplication area) having a highly uniform planar structure under severe variability of the employed semiconductor manufacturing process. In general, a junction surface has a smaller curvature radius (i.e., an acute angle) at an edge 114 of the p-n junction 110. Therefore, the electric field becomes stronger in that location. If the formed electric field is locally uneven, a breakdown will be induced at the higher electric field portion. A conventionally known SPAD array has a guard-ring structure, which surrounds the avalanche multiplication area in such a way as to prevent the breakdown at the edge thereof. Although the guard-ring structure can be modified in various ways, the guard-ring structure has a role of forming a low electric field area that surrounds the avalanche multiplication area. Therefore, a sufficiently large electric field difference can be maintained between the planar avalanche multiplication area 107 and the guard-ring (edge layer) 114. Thus, the SPAD can realize highly reliable operations even in a case where a semiconductor layer has properties that vary depending on the employed process.
The electric field in the guard-ring 114 is not sufficiently strong to induce avalanche multiplication. Therefore, carriers having reached the guard-ring 114 or carriers generated in the guard-ring 114 do not repetitively cause impact ionizations and cannot be detected in the Geiger mode. If the relationship between the magnitude of the electric field and the width of the depletion layer in the p-n junction is taken into consideration, the lateral width 112 of the depletion layer in the guard-ring 114 is larger than the vertical thickness 111 of the depletion layer at a central region of the SPAD. However, similar to time characteristics in photon detection, the vertical thickness ill of the depletion layer has a significant influence on the efficiency in the detection performed by the SPAD.
It is desired for carriers to be generated when light is absorbed at depletion layer wherein the avalanche multiplication occurs, because such primary carriers can generate a SPAD output signal with a higher time resolution. If carriers are generated when light is absorbed in quasi-neutral regions located above and/or beneath the depletion layer, the generated carriers slowly diffuse and may reach the depletion layer without causing any recombination. In this case, the carriers can generate an output signal, although the time resolution is lower. Such a low time resolution will deteriorate performance when high time resolution is required in the application (e.g., TOF).
The number of carriers per unit of depth generated in a silicon substrate reduces exponentially when the depth increases. The reduction speed depends on a wavelength-dependent light absorption coefficient. The long-wavelength light can penetrate deeply before it is completely absorbed, because the long-wavelength light has a lower absorption coefficient. To absorb and detect incident light having a longer wavelength comparable to the near infrared ray as much as possible, it is desired for the vertical thickness 111 of the depletion layer to beset as larger as possible.
The sensitivity of the conventional SPAD is dissatisfactory in the near infrared region. The sensitivity depends not only on the aperture ratio but also on the photon detection efficiency. According to the conventional guard-ring structure, if the vertical thickness 111 of the depletion layer is increased, the lateral width 112 of the depletion layer increases correspondingly. This leads to a reduction in the aperture ratio. Therefore, according to the conventional SPAD, the aperture ratio and the photon detection efficiency are in a trade-off relationship.
A guard-ring structure capable of increasing the aperture ratio is proposed in the prior art. The proposed guard-ring structure has a shallow trench isolation (STI) structure as a guard-ring and is usable in a conventional CMOS technology. The STI structure can substantially limit the size of the light-insensitive boundary of the avalanche multiplication area. It is expected that the small width of the STI can realize a higher aperture ratio, because this process specification is optimized. However, the above-mentioned technique is defective in the following two points. First, the crystal defect density is high at the interface region between the silicon and the STI. Therefore, it is conventionally known that this interface region has a high density of traps and recombination centers with a broad energy distribution. Accordingly, it is necessary to separate the interface region from the high electric field area. In the STI guard-ring approach, the interface region is in contact with the avalanche multiplication area. Therefore, the STI/silicon interface tends to cause false counts, i.e. dark counts. In practice, a dark count rate of about 1 MHz occurs. Further, the STI employed in the CMOS technology is mainly used to separate low-voltage transistors. The depth of the STI is extremely small (e.g., a few hundred nm). Accordingly, unless the process is customized, the STI cannot be used to limit the boundary of a SPAD having a depletion layer whose depth exceeds several hundred nm.
Further, there is a conventional SPAD having another structure. The structure is based on a backside illumination (BSI) technology to bond a wafer of a thinned SPAD array with another wafer including an interface circuit to realize a SPAD having a high aperture ratio. The structure is characterized by a buried layer having a continuous stepped structure. The stepped structure enhances the electric field in the SPAD and forms a planar avalanche multiplication area. The electric field formed by the stepped structure is a drift field. Light can be absorbed over a wide region larger than the high electric field region. Generated carriers can be collected by the drift field. However, the buried layer having the above-mentioned structure cannot be realized by the CMOS process. Therefore, a specialized apparatus and processes are required to form the above-mentioned stepped layer.
Further there is a conventional technique capable of increasing the aperture ratio of the SPAD. When the aperture ratio becomes lower, light detection efficiency decreases correspondingly. Therefore, the conventional technique uses a microlens array to converge incident light to the avalanche multiplication area in such a way as to increase the detection efficiency. However, the use of the microlens array is not effective in many low-light applications, because those applications require an optical system having a small F-number. Further, customization of the CMOS process is required to manufacture the microlens array. Therefore, manufacturing costs increase. Further, the size of a microlens required for the SPAD is greater than the size (typically less than 10 μm) of a microlens that can be formed using the present CMOS technology. Therefore, realizing such a large and thick microlens further increases manufacturing costs.
The present invention is directed to a technique capable of solving the trade-off relationship between the aperture ratio and the photon detection efficiency and intends to provide a SPAD that has excellent time responsiveness for long wavelength light comparable to the near infrared range. In particular, the present invention provides a SPAD to which a general semiconductor manufacturing method, such as a CMOS process, is applicable and can reduce manufacturing costs.